1. Field of the Invention
The present invention relates to a method of forming an isolation structure, and more particularly, to a method of forming a trench isolation structure in a semiconductor memory device.
2. Description of the Related Art
In a conventional semiconductor memory device, a trench isolation structure is used for inter-de-vice isolation. Such a structure does not encroach upon a channel width of the semiconductor memory device, so that the size of the semiconductor memory device can he reduced. The trench isolation structure also can prevent a latch-up in a CMOS device, improving the characteristics of the semiconductor memory device.
Using a conventional method, a uniform trench isolation structure is formed. A conventional trench isolation structure as shown in FIG. 1E includes a plurality of trenches 41, 42 and 43 formed on a semiconductor substrate 1, and burying materials 5a, 5b and 5c filled in the trenches 41, 42 and 43, respectively.
FIGS. 1A-1E show views illustrating a convention method of forming a trench isolation structure.
As shown in FIG. 1A, a pad oxide film 21, a polysilicon film 22, and a silicon nitride film 23 are sequentially formed on the semiconductor substrate 1 to serve as an etch stop layer and a polishing stop layer. Then the trenches 41, 42, and 43 are formed on the upper portion of the semiconductor substrate 1. Using a chemical vapor deposition (CVD), first, second and third silicon oxides 5a, 5b and 5c are respectfully filled in the trenches 41-43 and fourth through seventh silicon oxides 5d, 5e, 5f, and 5g are formed on the silicon nitride film 23 between the trenches 41-43.
To planarize the semiconductor substrate 1 shown in FIG. 1A, a chemical mechanical polishing (CMP) is performed on the entire upper surface of the semiconductor substrate 1. However, because the fourth silicon oxide 5d is wider than the fifth through seventh silicon oxides 5e-5g, a longer CMP process time is required to completely remove such silicon oxides.
As shown in FIG. 1B, in order to decrease the CMP process time required to remove the fourth silicon oxide 5d, a photoresist pattern 3 is formed on portions of the fourth silicon oxide 5d and over the other silicon oxides. Using the photoresist pattern 3, isotropic etching is performed to remove a central portion of the fourth silicon oxide 5d. As a result, marginal portions 50 of the fourth silicon oxide 5d remain as shown in FIG. 1C. In the isotropic etching process, 1/40 diluted hydrofluoric acid is used. In using the diluted hydrofluoric acid for etching, an etching speed ratio of the silicon oxide 5d and the silicon nitride film 23 is about 8:1.
As shown in FIG. 1D, the marginal portions 50 and fifth through seventh silicon oxides 5e-5g are completely removed by a CMP or an etchback using dry etching. Here, since the polishing speed ratio of the silicon oxides 5e-5g and 50 and the silicon nitride film 23 is about 5:1, the silicon nitride film 23 can he stably used as a polishing stopper. The silicon oxides 5e-5g serve as a burying material.
Then as shown in FIG. 1E, the silicon nitride film 23 is removed by a reactive ion etching (RIE) using a C.sub.4 F.sub.8 gas or by a wet etching using a hot phosphoric acid. The polysilicon film 22 is removed by a KOH solution and the pad oxide film 21 is removed by a hydrofluoric acid. As a result, the semiconductor substrate 1 having the trench isolation structure is fabricated.
However, the conventional method requires a complicated processing, such as, removing the silicon nitride film 23 after the CMP process. Further, during the CMP process, contamination of the semiconductor substrate 1 occurs.